Radiolocation system

ABSTRACT

To determine the locations of extraneous sources of radio waves, a central station omnidirectionally monitors a band of frequencies and, upon detecting a radio signal within such band, transmits information of its frequency to a plurality of peripheral stations which thereupon radiogoniometrically ascertain the angle of incidence of the signal having this frequency and relay the magnitude of this angle to the central station.

United States Patent [191 Bataille et al.

SECONDARY STATIONS RADIOLOCATION SYSTEM Inventors: Roger Bataille, Bures/Morainvilliers;

Francois P. Maison, Eaubonne; Pierre Paul Curvale, Verrieres-IeBuisson, all of France Assignee: Electronique Marcel Dassault, Paris,

France Filed: Mar. 25., 1968 Appl. No.: 716,704

Foreign Application Priority Data Mar. 24, 1967 France 67100193 US. Cl. 343/113 R, 343/100 CS lint. Cl Gls 3/72 Field of Search 343/100 CS, 1 13 I SC 20' T. i

RECEIVER 16 "MN I 13 15 smrmu l 1 e -H [C EVALVAT'ION RECElVER oumonrm usmoRx Nsrwonx COUPLER T1 23 y 21 z 1 14 y-ar mznom SCANNER CONTRDU.

" firmee l COUPLER s W 1 unuzmon -25 /Z\ T"I 1 1 \7 "Sl-im [56] References Cited UNITED STATES PATENTS 2,471,412 5/1949 Clark 343/113 3,181,160 4/1965 Pichafroy 343/113 Primary Examiner-Malcolm F. Hubler Attorney, Agent, or Firm-Karl F. Ross [5 7] ABSTRACT To determine the locations of extraneous sources of radio waves, a central station omnidirectionally monitors a band of frequencies and, upon detecting a radio signal within such band, transmits information of its frequency to a plurality of peripheral stations which thereupon radiogoniometrically ascertain the angle of incidence of the signal having this frequency and relay the magnitude of this angle to the central station.

20 Claims, 11 Drawing Figures SHEEIIBFB PATENTEDJANZSIQM P R Curvale gy ev is {Karl Attorney 'PAIENIEDJANZQIW 3,789.41 1

saw u or a R. Bafaille F. P.I Maison P. P. Curve/e INVENTORS.

q aR S a K GU Attorney PATENTEIJ 3,789,411

SHEEI 5 [IF 8 fl I -IL9 I 1' 1 @IN I l I I I i I I0 I p5 I l I l N I I I 1 I H l I I I A O I I l I I I I I i I I N l I -|c h I l RBafai/le E P. Maison P. P Curvale INVENTORS.

vI' lttomey PATENTEDJANZQIQH sum 5 or a Attorney RADIOLOCATION SYSTEM Our present invention relates to a radiolocation system having means for radiogoniometrically ascertaining the angle of incidence, usually within a horizontal plane, of radio signals from extraneous sources.

As is well known, an emitter of radio waves can be pinpointed with the aid of two or more spaced-apart receiving stations having crossed directive antennas, e.g., of the Adcock type, to determine the sine and cosine of the azimuth angle in terms of a selected reference direction (e.g. north-south). In order to minimize duplication of equipment at the several receiving stations, it is convenient to provide a main or central station having means for scanning a frequency band to be monitored and, upon detecting an emission from a source to be located, transmitting the frequency of that source to the associated secondary or peripheral receiving stations which thereupon ascertain the respective azimuth angles and relay that information to the main station for computation of the point of intersection of the several directions of incidence. One of these secondary stations may also be located at the main station itself.

The general object of our present invention is to provide a radiolocation system of this character having means for rapidly exchanging the frequency and azimuth information between the main and secondary stations so as to enable a detection of outlying radio sources emitting only for short periods.

Another object is to provide means at such secondary station for increasing the accuracy of the angular information delivered to the main station, with substantial elimination of errors due to divergences of circuit parameters.

A further object of our invention is to provide means in such system for automatically selecting, from among a number of extraneous transmitters operating within the monitored band, only those sources which were not previously pinpointed or which may have significantly altered their bearings since the last ascertainment of their position.

A radiolocation system according to our invention, designed to realize the aforestated objects and capable of operating fully automatically with unmanned equipment, comprises an'omnidirectional radio receiver at the main station which is also provided with means for periodically scanning the frequency band of the receiver output and, upon detecting an incoming signal from an outlying source anywhere within this band, transmitting information on the frequency of this signal (i.e. its location within the scanned spectrum) simulta neously to each of the several associated secondary stations whose directional antenna arrays work into receivers tunable by this information to generate a combination of electric magnitudes representative of the angle of incidence; the magnitude of this angle, advantageously in digitized form, is then relayed to the main station for conveyance to a Visualizer, computer or similar utilization means together with the corresponding frequency information already available at that station.

Since each secondary station thus operates on only one incoming radio signal at a time, its equipment can be relatively simple and, in a preferred embodiment, includes only the logic necessary for the instant evaluation of the radiogoniometric measurements taken,

without any need for prolonged storage of the results of these measurements.

According to a more specific feature of our invention, the electric quantities representing the two trigonometric functions sine and cosine" are transmit ted to an evaluation network over a pair of inter changeable channels which are switched during two measurements taken in immediate succession so as to minimize reading errors due to differences in the transmission characteristics of the two channels, the results of these two consecutive measurements being thereafter averaged to yield a single azimuthal value to be transmitted to the main station. In reducing these angle measurements to binary form, we prefer to assign to each bit of a binary word a value of 1122*" where k is any integer from Uthrough 8, the least-significant bit being thus equal to 11/256 which equals, roughly, 0.7.

'Another feature of this invention resides in the provision ofa coder which, with the aid of a comparison circuit connected to the outputs of two negativefeedback amplifiers, translates two voltages respectively proportional to sina and cosa (where a is the desired azimuth angle) into the binary equivalent a a 7 within the range from Q to 11/2. With such a coder, only the lower-order bits (starting wi ITi k 2) are derived directly from the measured sine and cosine values, the highest-order bits of weight w (k= 0) and 1r/2 (k= 1) being added on the basis of phase comparison between the individual outputs of the directional antennas and an omnidirectional signal synthesized therefrom. In this case, in computing the average or arithmetic mean of the binary values of two such angles, care must be taken to avoid the possibility of significant error when the two angles lie on opposite sides of the boundary between adjoining quadrants; a more specific feature of our invention, therefore, provides for a selective suppresion of the output of the summing logic dealing with these highest-order bits when the two angles are found to lie in different quadrants.

Other features of our invention relate to the selective reading of a memory at the main station, designed to pick up only those radio signals for evaluation which originate within a frequency channel not occupied during an immediately preceding scanning cycle so as to avoid an overloading of the equipment by repetitive tracing of transmitters already located, and to the overlapped processing of information read out from the memory to permit the transmission of information between the main and secondary stations at a relatively slow rate, with transmission from and to the main station preferably lasting substantially as long as the location of an indicated radiation source by the secondary stations; particularly this latter feature makes it possible to use tranmission lines of limited bandwidth, such as telephone lines, for inter-station communication.

The invention will be described in greater detail with reference to the accompanying drawing in which:

FIG. 1 is a block diagram of an entire radiolocation system embodying the present invention;

FIG. 2 is a block diagram of a secondary station forming part of the system of FIG. 1;

FIG. 3 is a more detailed diagram of certain components of the equipment shown in FIG. 2;

FIG. 4 is a time chart relating to the operation of the station shown in FIG. 2;

FIG. 5 is a more detailed diagram of another component shown in FIG. 2',

FIG. 6 is a graph used for explaining the operation of the arrangement shown in FIG.

FIG. 7 is a view generally similar to FIG. 2, illustrating the main station of the system of FIG. 1;

FIG. 8 is a timing diagram relating to the overall operation of the system;

FIG. 9 is another graph useful for an understanding of the operation of the assembly of FIG. 5;

FIG. 10 is a circuit diagram showing details of an element of FIG. 5; and

FIG. '11 illustrates a detail of an element forming part of the central station shown in FIG. 7.

Reference will first be made to FIG. 1 which shows a radiolocation system having a main or central station SC and a plurality or peripheral or secondary stations SR,, SR SR,,,. These stations are interconnected by two-way transmission lines T,, T T,,,, such as telephone lines, extending between the main station SC and each of the associated secondary stations.

The several secondary stations being identical, only station SR, will be described in detail hereinafter. This station comprises a receiver 11 provided with a directional antenna array 10 of one or more pairs of crossed Adcock aerials. Receiver 11 works into a goniometric network 13 responsive to a controller 14 which in turn receives timing signals and frequency information from the main station SC via the associated transmission line T, and a coupler 16 containing modulating and demodulating equipment. The output of network 13 is supplied to coupler 16 by way of an evaluation network 15.

The main station SC has a receiver 20 equipped with an omnidirectional antenna or antenna array 20' and working into a scanner 21. This scanner is controlled by a timer 22 which, in addition to furnishing synchronization signals to the secondary stations SR, SR,,,, controls a memory stage 23 as well as a utilization stage 25 having an output E for the control of a panoramic display or some other load designed to handle the information produced. A coupler 24 is the counterpart of coupler l6 and serves to route the incoming and outgoing messages from and to the associated transmission lines.

Details of station SR, have been illustrated in FIG. 2. Receiver 1 1 is here shown to comprise two antenna arrays 10 and 10" of wide and narrow base, respectivcly, for receiving radio signals in the lower and the higher frequency ranges of a spectrum extending be-' tween, say, 1 and 30 megacycles. A switching stage 33, operable by a tuning stage 52 in controller 14, selectively applies the output of either antenna array to a co-ordinate separator 32 which delivers the highfrequency oscillations from the selected array to the goniometric network 13 by way of feeder lines 34, 35 and 36. Line 34 carries the output of an Adcock antenna effective in the north-south direction so that the amplitude of this oscillation is proportional to cosa where a (see FIG. 9) is the angle included between the direction S of the incoming radio signal and the N-S reference line; similarly, line 35 carries the conjugate output of an east-west antenna having an amplitude proportional to sina. These antennas may be suitably shielded so as to be receptive only to signals from one half of the horizon, the other half being surveyed in each case by an oppositely oriented companion antenna as is well known in the art. Line 36, finally, carries an oscillation of the same frequency which is the vector sum of the two conjugate oscillations on lines 34 and and whose amplitude is therefore independent of the angle of incidence.

Lines 34 and 35 form the input terminals of a pair of interchangeable channels 37 37 bracketed by two electronic crossover switches 40 and 41; these switches are under the control of a sequencer 57 in network 15 which responds to pulses from a local timer 56 controlled from the central timer 22 via synchronizing pulses traversing the coupler 16. The first channel 37, includes a preselector 38, followed by a final selector 39,; corresponding selectors of the second channel 37 have been designated 38, and 39 A third channel 37 independent of switches 40 and 41, also has two such cascaded selectors 38,, and 39 Tuner 52 controls all the preselectors and all the final selectors in parallel. In the specific embodiment here contemplated, the preselectors may sift from the overall spectrum a frequency range 1 Mc wide, e.g., between 1 and 2 Mc; this range, in turn, is then broken up by the final selectors into 1,000 bands of l Kc each,

resulting in an intermediate frequency in the outputs of these channels within a predetermined band I Kc wide. Thus, the tuner 52 may include means for generating a first set of heterodyning frequencies, spaced 1 Mc apart, for the preselectors and a second set of heterodyning frequencies, spaced 1 Kc apart, for the final selectors; FIG. 2 shows for this purpose a stabilized local oscillator co-operating with a beat-frequency generator 51 to produce the desired heterodyning frequencies as selected by the tuner 52 under the control of a decoder 55 in network 15. This decoder, advantageously, converts the binary frequency identification from coupler 16 into a decimal value convenient for the control of an adjustable generator with 1,000 output frequencies. The i-f oscillations from channels 37,, 37 37,, yield, upon detection in network 13, a pair of voltages U,, U respectively proportional to cosa and sina, as well as quadrant-identifying signals O which are developed in a phase demodulator 58 for transmission to a coder 59' in network 15. The coder supplies the value of the measured angle a, in binary form, to a computer 59 whose output is fed to coupler 16 under the control of timer 56.

The several components of network 13, described above in connection with FIG. 2, are shown in still greater detail in FIG. 3. As particularly illustrated for channel 37, each of these channels includes, in addition to a first mixer 38, and a second mixer 39, representing the preselector and the final selector thereof, a filter 80, with a pass band of 1 Kc and an amplifier 81 for the output of this filter. Corresponding elements in channels 37, and 37,, have been similarly identified with subscripts 2" and 0, respectively. Channel 37,, also includes an automatic gain control 82 for its final amplifier 81 The output lines of these three channels have been designated 101,, 101 and 101 respectively. Line 101, is split into two branches 102, and 103,, respectively terminating at a squarer 104, and an isolating amplifier 115,; corresponding branches of line 101 lead to a squarer 104, and an isolating amplifier 115,. Squarers 104, and 104, convert the i-f oscillations from their respective channels into rectangular pulse trains which also control, via respective amplifiers 116, and 116,, the operation of a pair of ring demodulators 106, and 106, receiving the outputs of amplifiers 115, and 115,. Demodulators 106,

and 106 produce the aforementioned voltages U, and U appearing on respective leads 114, and 114 in-the output of crossover switch 41. Other output leads 107, and 107 of this switch apply the rectangular pulse trains from squarers 104,, 104 to two phase comparators 108,, 108 which also receive, via amplifiers 109, and 109 the amplitude-stabilized i-f oscillation from output lead 101 of channel 37 Each phase comparator 108, and 108 forming part of the demodulator 58, works into a pair of flip-flops 112,, 113, and 112 113 respectively. These flipflops have individual output leads 110,, 111, and 110 111 extending to the coder 59' of network they are also provided with resetting inputs connected to a timer-controlled source of short pulses d.

Crossover switch 40 has a pair of direct paths a, respectively connecting lines 34 and 35 with channels 37, and 37 and a pair of alternate paths b crossconnecting these lines and channels. Analogous paths between lines 105,, 105 and leads 107,, 107 through crossover switch 41 have been designated a and b. The latter switch further includes alternate connections a and 11" between the outputs of demodulators 106,, 106 and the conductors 114,, 114 carrying the voltages representative of the trigonometric functions cosa and sina. Letters a, a, a" and b, b and b" have also been used to designate the timing pulses which operate these switches to establish the respective paths.

FIG. 4 shows a chart in which the occurrence of switching pulses a, b, etc., has been plotted, along the abscissa, for a location cycle extending over a time of milliseconds as measured along the ordinate. At time 0, pulse a is generated to last for a period of 8 ms; 2 milliseconds after the termination of pulse a, pulse b comes into existence for a similar period. Pulses a, a" and b','b" occur during the second halves of pulses a and b, respectively. At instants t 8 ms and t= 18 ms, measured from the beginning of the cycle, resetting pulses d are generated together with clearing pulses c which serve to discharge any residual votages from the ring demodulators 106, and 106 these pulses c and d may have a duration of 0.1 ms or 100 us. All these pulses are produced by the sequencer 57 of network 15, shown in FIG. 2'.

In the operation of the system so far described, the occurrence of a pulse a applies the north-south output of receiver 11 to channel 37, and delivers the i-fsignal thereof to line 101,; concurrently, the east-west output of the receiver appears as an i-f signal on the line 101 Pulse a thereupon allows unit 108, to set either of the two associated flip-flops 112, and 113, in accordance with the phase relationship between the output of squarer 104, and the reference wave on lead 101,,, flipflop 112, responding to a positive phase relationship whereas flip-flop 113, is set in the presence of a negative phase relationship. The same kind of operation of phase comparator 108 with reference to the output of squarer 104 may set either of the associated flip-flops 112 and 113 Thus, an energization of leads 110,, 111,, 110 and 111 indicates, respectively, positive cosine, negative cosine, positive sine and negative sine. From the well-known relationship of these trigonometric functions, the coder 59' determines the quadrant in which the signal direction S (FIG. 9) is located. Voltages on leads 110, and 110 indicate the first quadrant (NW); voltages on leads 111, and 110 identify the second quadrant (SW); voltages on leads 111, and 111 define the third quadrant (SE); and, finally, voltages on leads 110, and 111 signify the fourth quardant (NE). These four voltage combinations, therefore, represent the quadrant-identifying signal Q mentioned in connection with FIG. 2. At the same time, pulse a" generates the voltages U, and U from the outputs of demodulators 106, and 106 connected to leads 114, and 114 respectively.

In the second half of the location cycle represented by the chart of FIG. 4, the same process is repeated with the north-south signal passing through channel 37 while the east-west signal travels through channel 37,. Because of the compensatory crossover at switch 41, however, conductors 110,, 111, and 114, will again carry the cosine voltages while conductors 110. 111 and 114 carry the sine voltages. In general, the voltages U, and U will vary but slightly, as a result of minor differences in the transmission characteristics of the two switchable channels, in the two halves of the cycle; if, however, the angle 0: lies in the vicinity of D, 7r/2,'n' 31r/2, the signal Q may shift from one quadrant to an adjoining quadrant in the presence of differences in transit time between these channels.

FIG. 5 shows the construction of the coder 59' receiving the output U,, U Q of demodulator 58. This coder comprises a logic matrix 203 for converting the signal Q into a pair of bits, of numerical weight 11' and 1r/2, stored in a 2-stage shift register 202. Leads 114, and 114 terminate at respective input stages 214, 220 ofa pair of identical 2-stage amplifiers 210, 211 whose output stages have been designated 216 and 222; feedback loops 232, 233 degeneratively couple the outputs of stages 216 and 222, represented by respective voltages U, and U,,, to the inputs of stages 214 and 220 which convert the effective input voltages U, U, and U U into a pair of intermediate voltages V,, V applied to two calculating networks 215, 221 respectively interposed between the two stages of each amplifier. Networks 215 and 221 are linear resistance pads, as conventionally used in digital/analog converters, adapted to multiply their input voltages V, and V by respective factors in the form of voltages of magnitude e and Z applied to their secondary inputs 226, 227 which are two outputs of a 7-stage binary shift register 225. The output voltages U, and U of amplifier 210 and 211 are fed via respective conductors 218 and 224 to input terminals 234, 235 of a comparator 219 which produces an error signal, proportional to the difference between these two voltages, at its output 236. This error signal is fed into a logic network 228 converting it into a 7-bit word to load the register 225 or to modify its contents.

The seven bits temporarily stored in register 225 define an angle, 6, within the range 0-n-l2 representing the multiplier delivered via output 226 to network 215;

the other multiplier 2, fed to network 221 via output 227, is the complement 1r/2 e of that angle. It will be understood that each of leads 226 and 227 represents a group of seven lines for transmitting the seven bits stored in register 225, or their complements, to respective terminals of the resistance matrices constituting the networks 215 and 221.

Each of these seven bits has a numerical weight given by the expression 2hr" where k is an integer ranging from 2 through 8; thus, the most-significant bit stored in register 225 represents an angle of 1r/4, or

45, whereas the least-significant bit equals IT/256, or 0.7 42'.

When the register 225 is empty, its output e is zero and its output Eequals 'rr/2 radians. If U is 0, indicating that sin a=a=0, no voltages will appear on either input of comparator 219 and no error signal will be generated, the contents of register 225 representing the true value of a. If, however, U has a finite value at the instant when logic network 228 receives an enabling pulse over a timer lead 212, an error signal on comparator output 236 causes the network 228 to feed in a value 6 representing a first approach to the value of angle a. The error signal then diminishes until 6 is substantially equal to or within the limits of precision established by the weight of the least-significant bit (here 17/256 radians). Thus, register 225 in its state of equilibrium contains a very close binary approximation of the magnitude of the angle of incidence a, it being, of course, possible to increase the degree of precision by adding further stages to the register.

The exact mechanism for equilibrating the register 225 will now be described.

Let G be the gain of each input stage 214, 220 of amplifiers 210 and 211, and let it be assumed that the gain of output stages 216, 222 is unity or has been merged with the output/input ratio of the associated calculating network 215, 221 so that and Furthermore, from the degenerative nature of the feedback through loops 232 and 233, it follows that V1= ab r) and whence U|IIU| GG E Y] and U nU G'/l CE [G(1r/2 e)/l G(-n-/2 6)] Functions Y, and Y have been illustrated in FIG. 6. They represent two symmetrical right hyperbolas with l/G,. respectivelyjthe ordinate s 1r/4, on which they intersect, is their line of symmetry.

Let us now consider the ratio rr/4 at the point Y 5, within the firstguad ranto s e s 11/2. For a certain (151116 of G the two curves nearly coincide to 5 degree sufficient to let us postulate, pursuant to equations (5), (6) and (7):

and since tane z (UK/U tana It will thus be seen that, with the proper value of G, e z 0: whenever the two output voltages U, and U are alike.

For certain angles, the identity of a and s will exist independently of the value of G. The case of a e 0 has already been discussed above. At the other limit of the range, not quite attainable with a finite number of bits, 01 e 1r/2 which follows from-the fact that E and U both vanish so that U, U 0. A third case is that of a e 1r/4, the two output voltages being again identical..

With any other angle, the proper value'of G can be determined from the requirement that In the case of a e 'rr/6, for example, substitution of the specific values in equation (ll) yields More exact computation furnishes an optimum value of 0.3534; with this value, the error is an approximately sinusoidal function of e having a period 1r/4 and a peak amplitude on the order of 2 minutes of arc.

Since the gain of amplifier stages 214, 220 is fractional, these stages can be considered as representing merely step-down voltage transformers for direct current; stages 216 and 222 can be omitted if the networks 215 and 221 produce the correct output voltages.

The substantial disappearance of the error signal on lead 236 causes the logic network 228 to emit an endof-coding signal on a conductor 213 to stimulate the timer 56, FIG. 2, to generate control pulses for the discharge of the registers 202, 225 into the computer 59 and for the processing of the azimuthal information in that computer; the leads carrying these pulses have been omitted in the drawing, with certain exceptions specified hereinafter.

Computer 59 includes a shift register 204, adapted to receive the nine bits from the combined registers 202, 225, and a full serial adder 205. The latter serves for the summing of an augend, i.e., the value of a (with inclusion of the two highest-order bits containing the quadrant information) determined during the first half of a 20-ms location cycle (see FIG. 4), and an addend, i.e., the magnitude [3 measured in the same manner during the second half of that cycle. After performing the nine shifts required for this summing operation, the adder carries out one further shift to the right, i.e., toward the less-significant digits, to yield the arithmetic mean of the sum, generally with a dropping of the last bit.

Owing to the manner in which the binary code for the azimuth angle is initially synthesized in the two registers 202 and 225, the combined numerical value of these nine bits does not always correspond to the magnitude of the angle in radians. Such correspondence exists in the first quadrant, in which the two highest bits are which can be represented by the notation (T 59 (see FlG. 9); in the second quadrant, however, defined by the notation 1 62 the order of the seven lower bits is reversed, all these bits returning to 0 for a= 17. In the third quadrant (H a the bits are again in their natural sequence, while in the fourth quadrant (0 m reversal occurs once more. The same relationship applies, of course, to the second angle [3 of the pair to be averaged. Thus, in view of the above-noted possibility of a shift from one quadrant to an adjoining one in the measuring of the two angles, the operation of the adder 205 must be modified with reference to the summing of the two highest-order bits to prevent possible error under such circumstances. This will now be explained in greater detail with reference to FIGS. 5 and 10.

Upon the completion of the coding of a in registers 202 and 225, atimer pulse on a lead 208 opens an AND gate 241 in the output of the latter register so that the nine digits of this azimuthal code can be serially transferred through an OR gate 242 to register 204 where they remain until the coding of B has come to an end. Thereafter, a timer pulse on a lead 209 unblocks two further AND gates 243, 244 in the output of register 225 and an AND gate 245 in the output of register 204; this delivers the augend a from register 204 and the addend B from registers 202, 225 to adder 205 and allows the sum 6 to be transmitted via OR gate 242 to register 204 where the tenth shift occurs and which is subsequently discharged, again under timer control, over a lead 207 also indicated. in FIG. 2.

FIG. shows the adder 205 as comprising two conventional half-adders 205, 205"; the associated augend and addend registers 204 and 220 225 have alsobeen illustrated, with omission of the AND gates 244, 245 seen in FIG. 5. At a particular stage of its operation, these registers deliver respective bits 01,, and B, representing the n"'-lowest digital position. The first seven bits, 01, through a, and B, through 1 are processed in the normal manner, with half-adder 205 de-' livering its output a,fi,,+a,,p, over a lead 251 to halfadder 205" while the carry a fi appears is delivered through on OR gate 265, together with the carry 7,, developed by half-adder 205" in an AND gate 266 to a lead 252 which includes a delay element 253 for preserving this carry, if any, for the next adding step as an output y,, The sum 6,, appears on an output lead 254 of an OR gate 267" supplied by two AND gates 268",

269 half-adder 205". Corresponding AND and OR gates of half-adder 205' have been designated 266' 269'. AND gates 268', 269' and 268", 269" are each provided with an inverter 270', 271 and 270", 271" in one of their inputs.

Lead 251 includes an AND gate 255 which is kept open during these first seven summing steps by control pulses P, P applied to it through an OR gate 256. At step No. 8, however, AND gate 255 remains blocked so that the sum 01 5 5 3 cannot be formed; this results in the reduction of the total by 1r/2. and therefore of the arithmetic mean by 1r/4, if the angles a and B lie in adjoining quadrants.

A lead 257, carrying the bit or is connected directly to an AND gate 258 which also receives, from a lead 259 energized by element 271, the inverted bit E,, via a delay element 260. A similar delay element 261 connects lead 257 to an AND gate 262 to deliver to it the bit 04 gate 262 further receives the undelayed in verted bit 5,, directly from lead 259. AND gates 258 and 262 work through an OR gate 263 into another AND gate 264 which is always blocked except during the ninth summing step when it receives a control pulse P on its other input; the output of gate 264, which can thus be defined by the notation 3 01,, a,,,,, is also applied through OR gate 256 to AND gate 255 so as to open the latter during this ninth step if angle a lies in either the second or the third quadrant. In such a case, summing proceeds normally at this stage even if the two angles lie on opposite sides of the N-S line; otherwise, i.e., if a is in one of the other two quadrants, the value 1r is dropped from the total so that the arithmetic mean is further reduced by 1r/2.

The significance of this arrangement will be described with reference to a few representative examples.

Case I: a 89, [3 92.

Angle a is defined by bits or 11'I256, a, 11/128, 01 1r/64, a 1/32, a IT/16, a 'rr/8, 01-, IT/4, a a =0.

Angle B is defined by bits [3, vr/256, B 0, B 1r/64, B 11/32, B 1r/16, B 17/8. B, WM, 8,, 1r/2, B 0.

The halved sum of the numerical weights of all these bits equals-190M256; this is a deviation of about 1r/4 from the obvious average value of 90%. The suppression of the product (1,8,, cures this significant error.

Case ll: a= 179, B= l82.

Here, a. 11/256, 01,, 77/2; B, 77/256, B If/1Z8, B 11. All other bits are 0. The numerical average would be I94 77/256, again deviating by about 1r/4 from the true mean value of l%. To eliminate this error, the product 8B8 is suppressed but the product 6:95,, is preserved.

Case III: a= 1, B=359.

All bits are 0 except q 1 =fi;=7r/256, pz =rrl2 and a 11. The computed average would be 19311/256, representing a departure of about 31r/4 from the true mean value of 0. This is remedied by the suppression of both products 01 B and 01 m.

We shall now refer to FIG. 7 for a detailed description of the central station SC. The receiver 20 thereof comprises, besid'esits omnidirectional antenna or antennas 20' which should have the same overall reception characteristics as the Adcock aerials of the secondary stations, a coupler 64 feeding a number of transmission lines 65 which lead to the assembly 21, 23 and to as many parallel assemblies of like character as are necessary to handle the entire frequency spectrum of, say, 30 Me to be monitored. The timing stage 22 may be common to all these assemblies.

Scanner 21 comprises a preselector 61, tuned to the desired megacycle band, and a final selector 62 in cascade therewith, the latter being controlled by a tuner 67' with the aid of a stabilized local oscillator 66 and a beat-frequency generator 67- in essentially the manner described for the units 13, 14 in FIG. 2. Tuner 67', operating under the control of a sequencer 69 in memory stage 23, may also periodically reset the preselector 61. Selector 62 works into a signal detector 63 which responds to incoming radiation within any of the 1000 l-Kc frequency channels within the band under consideration. Sequencer 69, responsive to clock pulses from a timing circuit 70 paced by the oscillator 66, is assumed to allot a time of 2 seconds to a 1,000-channel scanning cycle, corresponding to 2 ms for the exploration of a single channel; this corresponds to a clockpulse cadence of 500 bauds.

An electronic stepping switch 71 in unit 23, receiving the output of signal detector 63, addresses a test memory 72 which stores these signals for several scanning cycles in a manner more fully described hereinafter. A reader 74 repetitively samples the memory 72 and also serves to cancel theinformation stored therein, under the control-of a resetting-pulse generator 73, at certain intervals and under conditions specified below. Reader 74, when energized, actuates a corresponding stage of an address register 75 which, under the control of clock circuit 70, is then connected through a routing network 75 to a buffer register 76 while also delivering to coupler 24 a message identifying the frequency channel containing the signal which triggered the reader 74. After the secondary stations served by coupler 24 have responded to this message in the manner described above, the location of the signal source is entered in buffer register 76 for transmission to the output channel E conjointly with the frequency information previously stored in that register.

The memory 72 has as many pairs of binary storage elements, here 1,000, as there are frequency channels to be explored during each scanning cycle. One such pair of storage elements has been illustrated, by way of example, in FIG. 11 as two ferrite cores 90A, 908, designed to receive two bits A, B conveying the state of activity of its channel. A writing lead 91 is energized by switch 71 upon the detection of a radio signal in the associated frequency channel so .as to store a bit B therein; when the reader 74 next addresses this memory stage, it transmits a pair of switching pulses over two wires 92A, 92B (collectively designated 92) to the two elements 90A, 903 to read out the bit B which thereupon is promptly reinscribed, via a lead 93, upon the element 90A as a bit A. On the following sampling or reading cycle, therefore, this bit A is retrieved over the lead 92A without further reinscription. M

The reader 74 includes logic circuitry which .responds to only one of the four possible combinationof switching states of cores 90A and 90B, namely-the situation in which core 908 is set while core 90A is reset, thus indicating that a new radio signal was picked up in a previously unoccupied frequency channel. Whenever this occurs, the advance of the reading scan is. halted for a period long enough to enable the registra; tion of the channel information on the buffer register 76, and the concurrent transmission of that information to the associated secondary stations, in response to an output pulse D on a lead 94. In the typical. example under consideration, this interruption of the sampling cycle may last for a unit interval of 12 ms, equaling six clock cycles. Thus the average rate of advance of reader 74 will differ from that of scanning switch 7! and will vary with the number of new signals encountered during each sweep. v

Resetting unit 73 periodically transmits to reader 74, via a lead 95,.a cancellation pulse C which is .processed by the logic of the reader simultaneously with the channel-identifying bits A, B received over lead 92 but which is not inscribed on the cores of FIG. 11. This cancellation pulse inhibits the reinscription of a bit B on core A (as a new bit A) under certain conditions. i.e., when the latter core already was found set by a previous bit A. The cadence of these cancellation pulses C is a small fraction of the scanning rate of 500 bauds, 1/64 'tiiiisiii't rate so that up to about 16 memory stages can be cleared per second, the entire memory being thus resettable in a little over two minutes. By this means, any memory stage assigned to a channel occupied for an extended period is cleared to enable the retrieval of a new signal during the next reading cycle, with reevaluation of bearing information from the secondary stations to ascertain a possible change in the position of the corresponding source.

The following chart summarizes the aforedescribed mode of operation of the reader logic:

Bits Cancellation read out pulse response reinscription (lead 92) (lead (lead 94) (lead 93) K B c 5 I A F c i) I A B 6 ti A A B C D A K B (C) D A The parentheses in the second column indicate that the presence or absence of a cancellation pulse on lead 95 is inconsequential.

When the register 75 is seized by a pulse D on lead 94, it transmits the address (i.e. the frequency position within the band under exploration) of the monitored channel in binary form, as a-series of bits, to all the associated secondary stations during a subcycle equal to approximately half the length of a 20-ms unit interval; the retransmission of the corresponding hearing data to the main station occurs during a subcycle of similar duration. With about 10 ms available for the transmission of the 10 bits required to identify one among 1,000 frequency channels, and again for the conveyance of bearing information by nine bits as described above, ordinary telephone lines and similar voice-frequency links are adequate for this purpose.

FIG. 8 illustrates the full sequency of operations of our systems over a plurality of partly overlapping working cycles each extending over two unit intervals, or 40 ms, beginning with a clock pulse CP at a time 0 (bottom graph). At that instant, the address register 75 (seized a short time before by a pulse D from reader 74) delivers the data of a first selected channel W to all the peripheral stations and to an available stage of buffer register 76. At 12 ms, this transmission is terminated and register 75 is released; at substantially the same time, the advance of reader 74 is restarted to sample the next stage of memory 72. lf, as here assumed, this stage carries a new signal from its assigned channel X, the outpulsing of the corresponding data starts at ms, thus about midway within the location subcycle performed at the secondary stations; this location subcycle, already described in detail with reference to FIG. 4, lasts from 12 to 22 ms, its end coinciding with the termination of the first transmission subcycle for channel X and with the beginning of the second transmission subcycle for the previously selected channel W. It will be further assumed that the reader 74, upon resuming its hunt, skips seven stages of memory 72 but detects the presence of a signal from yet another channel Y at the eighth stage, ie at time 48 ms. Transmission of frequency information on that channel cannot start until the occurrence of another clock pulse CP at the beginning of the next unit interval, i.e., at time 60 ms. The processing of this information is shown to overlap another operating cycle which starts at time 78 ms with the selection of a further channel Z.

With this mode of operation, the buffer register 76 requires but a small number of stages which are alternately made available, by the routing circuit 75, to receive the messages from address register 75 as indicated in the second-lowest graph of FIG. 8; the incoming bearing information from all the associated secondary stations is registered in the same stage as the corresponding address information, to be read out concurrently therewith or in immediate succession as part of the final output E (FIGS. 1 and 7). Thus, the switching of buffer register 76 occurs only upon the coincidence of a clock pulse C? with a seizure of address register 75.

The various command pulses required for the stepping of the several shift registers and related operations at all the stations are derived from the same source as the clock pulses CP, i.e., the main oscillator 66 which may also serve as the local oscillator 50 of a secondary station merged with station SC.

It will thus be seen that we have provided a system capable of automatically searching for emitters of radio signals of initially unknown frequencies, anywhere within a predetermined range, and for locating these emitters with the aid of only enough equipment at each secondary station to insure the desired accuracy of the resulting bearing data. Naturally, our system is not limited to the determination of azimuth angles as specifically described above by way of example.

We claim:

ll. A radiolocation system comprising:

a main station provided with omnidirectional antenna means for receiving radio signals from outlying sources over a predetermined frequency band;

a plurality of secondary stations each having a goniometric array of directive antennas for receiving the same radio signals;

circuit means connected to the output of said directive antennas for deriving therefrom a set of electric variables representing correlated trigonometric functions of the angle of incidence of such signals with reference to a predetermined zero direction;

two-way transmission means between said main station and each of said secondary stations;

scanning means at said main station for periodically exploring said frequency band;

memory means at said main station for temporarily storing information relating to the frequency of an incoming radio signal received by said omnidirectional antenna means;

reading means at said main station for repetitively sampling said memory means;

first coupling means at said main station for delivering said information from said reading means via said transmission means to all said secondary sta tions simultaneously;

tuning means at each secondary station responsive to said information for selectively limiting the output of said circuit means to a measure of the angle of incidence ofa radio signal having the frequency indicated by said information;

evaluation means at each secondary station for determining the magnitude of said angle of incidence from the electric variables in the output of said circuit means;

second coupling means at each secondary station connected to said evaluation means for relaying said magnitude to said main station via said transmission means; and

utilization means at said main station for evaluating the magnitudes of angles of incidence simultaneously received from said secondary stations.

2. A system as defined in claim l wherein said electric variables include a first variable proportional to the cosine and a second variable proportional to the sine of said angle of incidence, said evaluation means being provided with separate channels for said first and second variables.

3. A system as defined in claim 2 wherein said first and second variables are the amplitudes of a first and second intermediate-frequency wave derived from the incident signal, the electric variables in the output of said circuit means further including a third intermediate-frequency wave synthesized from said first and second waves, each of said channels including phasecomparison means for deriving a quadrant-indentifying signal from the phase relationship between said third wave and said first and second waves.

4. A system as defined in claim 3, further comprising switchover means at each secondary station for interchanging said channels between a first and a second measurement of said angle of incidence, said evaluation means including logic for averaging the results of said first and second measurements.

5. A system as defined in claim 4 wherein said evaluation means comprises a coder for converting said amplitudes into a sequence of lower-order bits representing the magnitude of said angle of incidence within a single quadrant and for deriving from said quadrantidentifying signal a combination of higher-order bits for uniquely identifying said angle over a full circle.

6. A system as defined in claim 5 wherein said coder is operative to assign the numerical weight Tr to the highest-order bit and numerical weights of 'rr'2 to suecessive lower-order bits, k being an integer varying progressively from 1 to a value such that 1r/2" is on the order of magnitude of l".

7. A system as defined in claim 6 wherein said logic comprises adder means and circuitry responsive to variations between said highest-order bits on said first and second measurements, indicative of a change of quadrants, for selectively suppressing the output of said adder means in the summing of said higher-order bits.

8. A system defined in claim 6 wherein said evaluation means includes a pair of demodulators for said first and second intermediate-frequency waves to produce voltages proportional to said amplitudes, said coder including first and second amplifier means connected to receive said voltages from said demodulators, register means for temporarily storing a set of lower-order bits under the control of the outputs of said first and second amplifier means, and comparison means inserted between said register means and said first and second amplifier means for modifying the contents of said register means in response to an error signal derived from the difference between the outputs of said first and second amplifier means.

9. A system as defined in claim 8 wherein each of said amplifier means is provided with a negative-feedback loop extending from an output to an input thereof, further comprising a calculating network in said loop for multiplying an intermediate voltage from the amplifier output by a factor derived from said reguster means and for feeding the product to said comparison means.

10. A system as defined in claim 9 wherein said register means is provided with first output means for delivering a first multiplication factor to the calculating network of said first amplifier means and with second output means for delivering a second multiplication factor to the calculating network of said second amplifier means, said first and second factprs being mutually complementary values of positive angles.

11. A system as defined in claim 10 wherein each of said amplifier means has a gain of substantially 0.35.

12. A system as defined in claim 1 wherein said memory means comprises a multiplicity of pairs of binary storage elements respectively assigned to different frequency channels within said band, stepping means for periodically addressing said pairs of storage elements at a constant rate in synchronism with the operation of said scanning means for the inscription of signal information therein and ata different rate for sampling by said reading means, said stepping means being operative to inscribe the signal information of any frequency channel in one storage element of a corresponding pair during a given scanning cycle and for shifting the information to the other storage element of the pair during an immediately following scanning cycle preparatorily to possible inscription of like signal information in said one storage element, and logic circuitry for energizing said reading means only in response to a combination of states of the storage elements of any pair indicating the occurrence ofa radio signal in a frequency channel not occupied during an immediately preceding scanning cycle.

13. A system as defined in claim 12 wherein said memory means further includes resetting means for periodically canceling the signal information inscribed in any pair having both storage elements set by signal information received in consecutive scanning cycles.

14. A system as defined in claim 13 wherein said resetting means is controlled by said stepping means to operate at a fraction of the operating rate of said scanning means.

15. A system as defined in claim 12 wherein said main station is provided with an address register scannable by said reading means for delivering to said transmission means a frequency code representing a selected frequency channel upon the energization of said reading means in response to signal information inscribed in an element of the pair assigned to such frequency channel.

16. A system as defined in claim 15 wherein said stepping means is operative to halt the sampling of said memory means by said reading means for a fraction of a scanning cycle upon energization of said reading means, further comprising a buffer register connected to receive said frequency code from said address register for temporary storage and to receive from said transmission means the magnitude of said angle of incidence as determined by each secondary station.

17. A system as defined in claim 16 wherein said stepping means comprises a source of timing pulses defining a succession of unit intervals each less than an operating cycle measured from the energization of said reading means to the reception of the corresponding magnitude by said buffer register, said fraction of a scanning cycle being substantially equal to a unit interval whereby sampling of said memory means by said reading means can be restarted for overlapping processing of signal information from different frequency channels.

18. A system as defined in claim 17 wherein said operating cycle consists of two transmission subcycles each substantially equal to half a unit interval and a location subcycle substantially equal to one unit interval.

19. A system as defined in claim 18 wherein said scanning means is operative to explore each frequency channel of said band during a minor fraction of said unit interval.

20. A system as defined in claim 19 wherein said unit interval is on the order of tens of milliseconds, said minor fraction being on the order of milliseconds. 

1. A radiolocation system comprising: a main station provided with omnidirectional antenna means for receiving radio signals from outlying sources over a predetermined frequency band; a plurality of secondary stations each having a goniometric array of directive antennas for receiving the same radio signals; circuit means connected to the output of said directive antennas for deriving therefrom a set of electric variables represEnting correlated trigonometric functions of the angle of incidence of such signals with reference to a predetermined zero direction; two-way transmission means between said main station and each of said secondary stations; scanning means at said main station for periodically exploring said frequency band; memory means at said main station for temporarily storing information relating to the frequency of an incoming radio signal received by said omnidirectional antenna means; reading means at said main station for repetitively sampling said memory means; first coupling means at said main station for delivering said information from said reading means via said transmission means to all said secondary stations simultaneously; tuning means at each secondary station responsive to said information for selectively limiting the output of said circuit means to a measure of the angle of incidence of a radio signal having the frequency indicated by said information; evaluation means at each secondary station for determining the magnitude of said angle of incidence from the electric variables in the output of said circuit means; second coupling means at each secondary station connected to said evaluation means for relaying said magnitude to said main station via said transmission means; and utilization means at said main station for evaluating the magnitudes of angles of incidence simultaneously received from said secondary stations.
 2. A system as defined in claim 1 wherein said electric variables include a first variable proportional to the cosine and a second variable proportional to the sine of said angle of incidence, said evaluation means being provided with separate channels for said first and second variables.
 3. A system as defined in claim 2 wherein said first and second variables are the amplitudes of a first and second intermediate-frequency wave derived from the incident signal, the electric variables in the output of said circuit means further including a third intermediate-frequency wave synthesized from said first and second waves, each of said channels including phase-comparison means for deriving a quadrant-indentifying signal from the phase relationship between said third wave and said first and second waves.
 4. A system as defined in claim 3, further comprising switchover means at each secondary station for interchanging said channels between a first and a second measurement of said angle of incidence, said evaluation means including logic for averaging the results of said first and second measurements.
 5. A system as defined in claim 4 wherein said evaluation means comprises a coder for converting said amplitudes into a sequence of lower-order bits representing the magnitude of said angle of incidence within a single quadrant and for deriving from said quadrant-identifying signal a combination of higher-order bits for uniquely identifying said angle over a full circle.
 6. A system as defined in claim 5 wherein said coder is operative to assign the numerical weight pi to the highest-order bit and numerical weights of pi .2 k to successive lower-order bits, k being an integer varying progressively from 1 to a value such that pi /2k is on the order of magnitude of 1*.
 7. A system as defined in claim 6 wherein said logic comprises adder means and circuitry responsive to variations between said highest-order bits on said first and second measurements, indicative of a change of quadrants, for selectively suppressing the output of said adder means in the summing of said higher-order bits.
 8. A system defined in claim 6 wherein said evaluation means includes a pair of demodulators for said first and second intermediate-frequency waves to produce voltages proportional to said amplitudes, said coder including first and second amplifier means connected to receive said voltages from said demodulators, register means for temporarily storing a set of lower-order bits undEr the control of the outputs of said first and second amplifier means, and comparison means inserted between said register means and said first and second amplifier means for modifying the contents of said register means in response to an error signal derived from the difference between the outputs of said first and second amplifier means.
 9. A system as defined in claim 8 wherein each of said amplifier means is provided with a negative-feedback loop extending from an output to an input thereof, further comprising a calculating network in said loop for multiplying an intermediate voltage from the amplifier output by a factor derived from said reguster means and for feeding the product to said comparison means.
 10. A system as defined in claim 9 wherein said register means is provided with first output means for delivering a first multiplication factor to the calculating network of said first amplifier means and with second output means for delivering a second multiplication factor to the calculating network of said second amplifier means, said first and second factprs being mutually complementary values of positive angles.
 11. A system as defined in claim 10 wherein each of said amplifier means has a gain of substantially 0.35.
 12. A system as defined in claim 1 wherein said memory means comprises a multiplicity of pairs of binary storage elements respectively assigned to different frequency channels within said band, stepping means for periodically addressing said pairs of storage elements at a constant rate in synchronism with the operation of said scanning means for the inscription of signal information therein and at a different rate for sampling by said reading means, said stepping means being operative to inscribe the signal information of any frequency channel in one storage element of a corresponding pair during a given scanning cycle and for shifting the information to the other storage element of the pair during an immediately following scanning cycle preparatorily to possible inscription of like signal information in said one storage element, and logic circuitry for energizing said reading means only in response to a combination of states of the storage elements of any pair indicating the occurrence of a radio signal in a frequency channel not occupied during an immediately preceding scanning cycle.
 13. A system as defined in claim 12 wherein said memory means further includes resetting means for periodically canceling the signal information inscribed in any pair having both storage elements set by signal information received in consecutive scanning cycles.
 14. A system as defined in claim 13 wherein said resetting means is controlled by said stepping means to operate at a fraction of the operating rate of said scanning means.
 15. A system as defined in claim 12 wherein said main station is provided with an address register scannable by said reading means for delivering to said transmission means a frequency code representing a selected frequency channel upon the energization of said reading means in response to signal information inscribed in an element of the pair assigned to such frequency channel.
 16. A system as defined in claim 15 wherein said stepping means is operative to halt the sampling of said memory means by said reading means for a fraction of a scanning cycle upon energization of said reading means, further comprising a buffer register connected to receive said frequency code from said address register for temporary storage and to receive from said transmission means the magnitude of said angle of incidence as determined by each secondary station.
 17. A system as defined in claim 16 wherein said stepping means comprises a source of timing pulses defining a succession of unit intervals each less than an operating cycle measured from the energization of said reading means to the reception of the corresponding magnitude by said buffer register, said fraction of a scanning cycle being substantially equal to a unit interval whereby sampling of said memory means by said reading means can be restarted for overlapping processing of signal information from different frequency channels.
 18. A system as defined in claim 17 wherein said operating cycle consists of two transmission subcycles each substantially equal to half a unit interval and a location subcycle substantially equal to one unit interval.
 19. A system as defined in claim 18 wherein said scanning means is operative to explore each frequency channel of said band during a minor fraction of said unit interval.
 20. A system as defined in claim 19 wherein said unit interval is on the order of tens of milliseconds, said minor fraction being on the order of milliseconds. 